From the birth of the first integrated circuit at 1960, the number of devices on a chip has grown in an explosive increasing rate. The progress of the semiconductor integrated circuits has step into ULSI (ultra large scale integration) level or even higher level after almost four decades of developments. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. Integrated circuits devices like transistors, capacitors, and connections must be greatly narrowed accompanying with the advancement. The increasing packing density of integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every element or device needs to be formed within smaller area without influencing the characteristics and the operations of the integrated circuits. The demands on high packing density, low heat generation, and low power consumption devices with a good reliability and a long operation life must be maintained without any degradation in the function. These achievements are expected to be reached with the simultaneous developments and advancements in the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies, namely the big five key aspects of semiconductor manufacturing. The continuous increase in the packing density of the integration circuits must be accompanied with a shrinking minimum feature size. With present semiconductor manufacturing technology, the processes with a generally one-third micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer or even nanometer sizes are highly demanded.
Transistors, or more particularly metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices in the integrated circuits with the high performance. However with the continuous narrowing of device size, the sub-micron scale MOS transistors have to face so many risky challenges. As the MOS transistors become narrower and thinner accompanying with shorter channels, problems like the junction punchthrough, the leakage, and the contact resistance, cause the reduction in the yield and reliability of the semiconductor manufacturing processes.
For developing future high speed ULSI circuits, the MOSFETs with an ultra-short channel, the self-aligned silicided contacts, and the extended ultra-shallow source/drain junction are required. In the article "CMOS Technology Scaling, 0.1 .mu.m and Beyond" proposed by B. Davari (in IEDM Tech. Dig., p. 555, 1996 IEEE), a projection of CMOS technology scaling and the expected performance, density, and power improvements are presented. To scaling the CMOS technologies down to the sub one-tenth micrometer regime, significant improvements in the silicon chip performance must be addressed with the solution for the threshold voltage non-scalability, interconnect RC delays, increased soft error rate and power density. The five modules including the gate stack, the gate dielectric, the source/drain, the isolation and the channel profile are the key technology elements for deep sub-micrometer CMOS devices.
However, it is difficult to define the gate length to be below 0.1 .mu.m due to the limitation of current optical lithography. The investigation of J. Tanaka et al. ("A Sub-0.1 .mu.m Grooved Gate MOSFET with High Immunity to Short Channel effects", in IEDM Tech. Dig., p. 537, 1993 IEEE) disclosed that the phase-shifted lithography followed by the self-aligned side wall oxide film formation must be utilized to enable a spacing less than 0.1 .mu.m for the gate.
The self-aligned silicidation technology is a vital application to improve the operation speed of the ULSI/VLSI MOS devices in manufacturing the sub-micron feature size semiconductor devices. Unfortunately, there exists some trade-offs in employing the technologies like self-aligned silicide. In general, the self-aligned silicidation process results a high junction leakage coming from the metal penetration. The metal penetration into the silicon substrate spikes the junction and/or the residual metal to cause the leakage problem. The silicide across the LDD spacer, which is not totally removed after the salicidation, causes the bridge between the adjacent devices like the gate and the source/drain regions. The detailed negative effects of the self-aligned silicidation technology on sub- micrometer devices are illustrated in the article of C. Y. Lu et al. ("Process Limitation and Device Design Tradeoffs of Self-Aligned TiSi.sub.2 Junction Formation in Submicrometer CMOS Devices", in IEEE Trans. Electron Devices, vol. ED-38, No. 2, 1991) The device design tradeoffs for a shallow junction with a salicide structure is proposed. Process limitations of both junction formation schemes for sub-micrometer application and future scaling down are also established in the work.